Table of Contents

Differences Between Master Clock, Generated Clock, and Virtual Clock

Term Definition Purpose PrimeTime Command(s) for Clock Generation
Master Clock The primary clock signal that drives the sequential elements in a design. Provides the timing reference for the entire design and synchronizes the operation of all sequential elements. N/A (typically specified as an input to PrimeTime)
Generated Clock A derived clock signal generated from the master clock using clock dividers, phase-locked loops (PLLs), etc. Used to operate specific blocks or modules in a design that require a different frequency or phase relationship. create_generated_clock, derive_pll_clock
Virtual Clock A logical clock representation used for timing analysis that may not have a direct physical counterpart. Helps model the behavior of paths where there is no direct clock signal, such as asynchronous or combinational paths. N/A (virtual clocks are defined within the SDC constraints)

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