||The primary clock signal that drives the sequential elements in a design.
||Provides the timing reference for the entire design and synchronizes the operation of all
||N/A (typically specified as an input to PrimeTime)
||A derived clock signal generated from the master clock using clock dividers, phase-locked loops
||Used to operate specific blocks or modules in a design that require a different frequency or
||A logical clock representation used for timing analysis that may not have a direct physical
||Helps model the behavior of paths where there is no direct clock signal, such as asynchronous
or combinational paths.
||N/A (virtual clocks are defined within the SDC constraints)